1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including complementary transistors, i.e., N-channel transistors and P-channel transistors, that comprise a high-k metal gate electrode structure in combination with epitaxially grown materials, such as strain-inducing semiconductor alloys, formed in the drain and source areas.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a very large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, most of the integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different silicon regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performing subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material for gate insulation layers that separate the gate electrode, frequently made of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. That is, conventionally, the thickness of the silicon dioxide layer has been correspondingly reduced to provide the required capacitance between the gate electrode and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. The relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may, therefore, reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher, may be used, for instance, in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials may also have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials in combination with the high-k dielectric material. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided.
The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence in order to adjust an appropriate work function for the transistors of different conductivity type and due to the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, one of which, referred to as replacement gate approach, includes processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and providing a highly conductive electrode metal.
In addition to providing sophisticated gate electrode structures, transistor performance may also be significantly enhanced by using a strain component in the channel region of at least one type of transistor, such as in P-channel transistors. It is well known that providing a compressive strain component along the current flow direction in a silicon channel region having a standard crystalline configuration may result in superior mobility of holes in the channel region, thereby also improving the drive current capability of the P-channel transistor. For this reason, a plurality of strain-inducing mechanisms have been developed, wherein one promising approach may be based on a strain-inducing semiconductor alloy, which is embedded into the active region of P-channel transistors after patterning the gate electrode structure. To this end, cavities may be formed in the active region laterally adjacent to the gate electrode structure and the cavities are subsequently refilled with a strain-inducing semiconductor alloy, such as a silicon/germanium material, which is grown in a strained state that in turn induces a desired compressive strain component in the channel region. The strain-inducing silicon/germanium material may be deposited on the basis of selective epitaxial growth techniques, in which process parameters are adjusted such that significant material deposition is restricted to crystalline silicon areas, while any material deposition on dielectric surface areas is suppressed. In order to avoid undue material growth on the gate electrode structures, the polysilicon material has to be reliably confined at least during the selective epitaxial growth process. For this purpose, the gate electrode structures are typically provided with a dielectric cap material, such as a silicon nitride material, and a silicon nitride spacer layer is typically provided so as to cover the N-channel transistors, while the silicon nitride spacer layer is patterned into sidewall spacer elements at the gate electrode structure of the P-channel transistor, wherein, in the same etch sequence, the corresponding cavities are also formed in the active region of the P-channel transistor.
Since the dielectric cap material has to be removed in a later manufacturing stage, i.e., during the replacement gate approach in order to expose the placeholder polysilicon material, which is typically accomplished by performing a complex planarization process based on chemical mechanical polishing (CMP) recipes, any asymmetry introduced during the overall process flow with respect to the exposure of the dielectric cap layers of P-channel transistors and N-channel transistors may also result in significant variabilities upon performing the replacement gate approach. For example, a significantly different thickness of the dielectric cap layer, which may be caused by the incorporation of the strain-inducing semiconductor material selectively in the P-channel transistor, may, therefore, result in pronounced irregularities upon exposing the polysilicon material during the replacement gate approach. For example, minute silicon nitride residues or any other dielectric residues that may still be present on top of the polysilicon material in some gate electrode structures may also lead to an incomplete removal of the polysilicon material, thereby significantly altering the characteristics of the resulting high-k metal gate electrode structures.
Moreover, upon further reducing the overall transistor dimensions, any performance-enhancing mechanisms, such as the strain-inducing semiconductor alloy provided in the P-channel transistors, may have an increased effect on the overall transistor performance. Therefore, the strain-inducing efficiency in the P-channel transistor is typically increased, for instance, by increasing the germanium concentration, reducing the lateral offset of the strain-inducing silicon/germanium material from the channel region and the like, wherein, however, any such efficient mechanisms for enhancing performance are not available for N-channel transistors, or any such mechanisms are significantly less efficient. Consequently, it has been proposed to enhance characteristics of N-channel transistors by providing a semiconductor alloy, for instance on the basis of a silicon/phosphorous composition, in order to provide overall superior electronic characteristics, for instance with respect to conductivity and the like. To this end, selective epitaxial growth techniques may be applied at any appropriate manufacturing stage, wherein, however, presently available process strategies may result in even increased non-uniformities between N-channel transistors and P-channel transistors, for instance, with respect to applying a replacement gate approach by efficiently exposing the placeholder polysilicon material.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which a strain-inducing semiconductor material may be efficiently incorporated in P-channel transistors, whereas an appropriate semiconductor alloy may be incorporated into the N-channel transistors, while avoiding or at least reducing the effects of one or more of the problems identified above.